\section{Solution}
The main task of this assignment was connecting the external signals to the MIPS-cpu, and creating missing internal components needed for implementing the required functionality.\\

\subsection{Connecting and creating the internal components} % (fold)
As mentioned in the introduction, the VHDL code for the processor was partly finished (ALU and Instruction- and Data Memory) along with the surrounding hardware. To complete the design, the following internal components had to be created:

\begin{itemize}
	\item Multiplexors
	\item Control unit
	\item Sign extend
	\item ALU-control unit
\end{itemize}

ISE Project Navigator proved a valuable tool in visualizing the design and helped locating errors. The final implementation can be viewed in Appendix \ref{RTL} 

All the internal signals connecting the components needed to be created. Most of these were made simply by connecting two separate pins in the port mapping of a unit, but some of them needed more logic. The PC is an example of a signal needing extra logic associated with it to behave as required.

\subsubsection{Program Counter (PC)}
The program counter is the signal in the MIPS-processor with most logic connected to it. The PC can be set by three different sources; either by the old PC, by a branch address, or by a jump address. The datapath of the PC runs through two multiplexors; the first choosing if the branch signal or old PC + 1 should go to the next one, the second choosing if the result from the previous multiplexor or the jump address should be sent to the \emph{instr\_memory\_address} signal, hence deciding where in memory to look for the next instruction.

\subsubsection{Control unit}
The control unit is responsible for setting all the control signals, hence controlling the behavior of the entire system. It has one input, namely the opcode gotten from the top bits of the current instruction (see Appendix \ref{MIPS_SHEET}).\\

The implementation of the control unit is quite basic. For each of the implemented instructions the control unit needs to set the control signals accordingly. A fraction of the control unit is included below. See CONTROL\_UNIT.vhdl for the full implementation.\\

\begin{lstlisting}[language={VHDL}]
begin
	if opcode = "100011" then -- Load Word
		RegDst 		<= '0';
		RegWrite 	<= '1';
		ALUsrc 		<= '1';
		ALUop 		<= "00";
		Branch 		<= '0';
		MemWrite 	<= '0';
		MemToReg 	<= '1';
		Jump			<= '0';
		Stall 		<= '1';
	elsif opcode = "101011" then -- Store Word
	...
	elsif opcode = "000100" then -- Branch Equal
	...
	elsif opcode = "000010" then -- Jump
	...
	elsif opcode = "000000" then -- ALU function
	...
	elsif opcode = "001111" then -- LOAD immediate
	...
	else -- No Operation
	...
	end if;
\end{lstlisting}

\subsubsection{Multiplexors}
When two signals connect to a single line, a multiplexor is needed to avoid burning the single line. Multiplexors take two input signals (or more) and select which input line to forward to the output. To make this decision the multiplexor depends on a control signal from the control unit.\\

Five multiplexors were needed in the implemented design:

\begin{description}
  \item[Register destination] \mbox{}\\Forward bits 20-16 or 15-11 from the instruction to the write register.
  \item[ALU source] \mbox{}\\Choose whether the second input to the ALU should be read from \emph{read\_data\_2} or bits 15-0 from the instruction.
  \item[Memory to register] \mbox{}\\Choose between the ALU result and data from the memory to forward to the register.
  \item[PC Branch] \mbox{}\\Sets the PC according to whether the instruction is a branch and if the zero flag from the ALU is set.
  \item[PC Jump] \mbox{}\\Sets the PC according to whether the instruction is a jump.
\end{description}

Implementing these multiplexors was done by first setting up the signals needed, and then creating a process with both the in-signals in its sensitivity list, which in turn sets the out-signal in an if statement (or some other conditional).

\subsubsection{Miscellaneous units}
Other units that were implemented:

\begin{description}
  \item[Sign Extender] \mbox{}\\Extends the 16 bits taken as input by filling the left half with zeros or ones, depending on the leading bit.
\item[ALU control unit] \mbox{}\\Uses the ALUop signal set by the control unit and decides if the ALU should perform the operation defined in the bottom 6 bits in the instruction or one defined by the ALU control unit (used in load/store).
\end{description}

\subsection{Connecting the external signals} % (fold)
\label{sub:implementing_emphprocessor_enable}
To get the processor working, the signals sent to/read from it by the external framework needed to be connected. Their use also needed to be right according to the specification. This is a description of the implementation of some of them:

\begin{description}
  \item[clk]The clock signal is added to the sensitivity list of the two processes that initiates the data path in the system (reading from instruction memory and reading the PC).
\item[processor\_enable]Processor enable is added to the same sensitivity lists as the clock signal, and everything done in those two processes depends on the processor\_enable signal being asserted.
\item[imem\_data\_in]This signal is connected to the result from the ALU. In the port mapping the units directly attached to it extracts the bits from it that is needed.
\item[dmem\_address]This signal is connected to the result from the ALU. When dmem\_write\_enable is low this will be the address read from.
\item[dmem\_address\_wr]The result from the ALU is sent to this signal. When dmem\_write\_enable is high this will be the address written to.
\item[dmem\_data\_out]This signal contains the data being written to the data memory. It is connected to the \emph{read\_data\_2 signal}.
\item[dmem\_data\_in]This signal contains the data read from memory. It is connected to the MemToReg-multiplexor, which chooses if the ALU-result or the data read from data memory should be sent back to the registers.
\item[dmem\_write\_enable]This signal is controlled by a multiplexor. The multiplexor chooses if the signal from the control unit or "0" should be used. The signal from the control unit is only used when the status is set to "execute". 
\end{description}

\subsection{State machine}
\label{state_machine}
The processor was implemented using a state machine with three states. Fetch, execute and stall. Each state corresponds to one clock cycle. In the fetch states, the program counter points to the current instruction than is being fetched by the instruction memory. The state machine then transitions to the execute state on the next cycle, where the current instruction is now ready. In the execute state all the interesting things happen inside the cpu in a single cycle. If the current instruction is a load or store instruction the state machines transitions to a stall state while the data is being loaded or stored to data memory. Then the state machine goes back to the fetch state.

% subsection implementing_emphprocessor_enable (end)

